1. Field of the Invention
The present invention relates to a test apparatus for memory and a test method thereof.
2. Description of the Related Art
As a main storage unit of a computer such as a personal computer, workstation, etc., DRAM (Dynamic Random Access Memory) is employed. DRAM uses a capacitor to hold charge, thereby holding data that is 0 or 1. The charge thus stored in the capacitor is discharged via a discharge path. Accordingly, there is a need to repeatedly perform a refresh operation, in which the data thus stored is temporarily read out and the data thus read out is written again, at a rate of several times per second.
Such a refresh operation is required in the DRAM testing process. Thus, a DRAM test apparatus mounts an algorithmic pattern generator (ALPG) having a timer configured to instruct the DRAM that is the device under test (DUT) to generate a refresh pattern.
The timer generates an interrupt signal which is an instruction to generate a refresh pattern at regular intervals. Typically, the cycle in which a refresh pattern is allowed to be generated within a test pattern generating program configured to test the DUT corresponds to the timing at which the DUT enters the idle state (access waiting state). The test apparatus includes an ALPG program counter having a function of detecting whether or not an interrupt signal occurs at this timing, and a function of generating an interrupt subroutine configured to generate a refresh pattern. In the active state of the DUT (the state in which the DUT is accessed), such an arrangement does not allow a refresh pattern to be generated. Thus, such a refresh pattern is not generated before the cycle enters the idle state cycle.
With conventional program counter circuits, in a case in which the interrupt signal is asserted twice or more when the DUT is accessed for a long period of time, only the first assertion event is held. This leads to a problem in that the refresh operation is performed only once after the cycle enters the cycle in which the refresh operation is allowed. Because of this, situations arise in which the number of times the refresh operation is performed during execution of the test pattern operation is insufficient, resulting in the stored data being damaged. In general, DRAM data is not damaged even if the refresh rate is slightly less than standard. However, depending upon the test conditions such as the voltage and temperature, and the individual difference in properties of the DUTs, in some cases, the data is damaged, and in some cases, the data is not damaged, even if the test is executed using the same test pattern. In particular, in a case in which the data has been damaged, it is difficult to identify the cause of the damage.